The present invention concerns a method of controlling the synchronization in a data packet communication network having at least two serial communication buses (D, E) interconnected by a bridge and each defining successive time cycles each having a duration specific to the said bus under consideration, the said method having the following steps:
detection of a relative drift between the respective cycles of the said at least two serial communication buses,
transmission of a command for modifying the duration of the cycle of one of the said at least two serial communication buses.
Communication networks are known which are formed from a number of serial communication buses in accordance with the IEEE 1394 standard.
These buses are organized as a network, that is to say they are interconnected by items of interconnection equipment which are referred to as xe2x80x9cbridgesxe2x80x9d.
The bridges connecting serial communication buses form more particularly the subject of the P1394.1 standard which is in the process of discussion.
A bridge is an item of equipment composed of two xe2x80x9cportalsxe2x80x9d which makes it possible to interconnect two 1394 buses. A xe2x80x9cportalxe2x80x9d is a set of 1394 ports belonging to the same 1394 bus.
The bus network thus forms a structure with a tree hierarchy in which one of the buses is considered as the upper bus, referred to as the xe2x80x9crootxe2x80x9d bus, from which the various other buses constituting the branches of the structure with a tree hierarchy extend.
Each serial communication bus of such a network interconnects various peripherals such as printers, computers, servers, scanners, video recorders, decoders (known by the term xe2x80x9cset top boxesxe2x80x9d), televisions, digital cameras, video cameras, digital photographic equipment etc.
These peripherals are generally referred to as nodes.
On each serial communication bus of the network, each peripheral or node has an internal clock from which so-called clock pulses are generated at a so-called clock frequency, for example equal to 24.576 MHz.
On each serial communication bus of the network, one of the nodes is referred to as the xe2x80x9cCycle Masterxe2x80x9d and the xe2x80x9cCycle Masterxe2x80x9d node of the xe2x80x9crootxe2x80x9d bus is referred to as the xe2x80x9cNet Cycle Masterxe2x80x9d.
Moreover, all xe2x80x9cCycle Masterxe2x80x9d nodes of the network have a characteristic which is specific to them, since it depends on the frequency of their internal clock, from which the duration of a xe2x80x9creference periodxe2x80x9d or xe2x80x9ccyclexe2x80x9d is defined.
The duration of the cycle denoted by T is equal to an integer number ninit of dock pulses common or otherwise to all the buses and which is multiplied by the inverse of the frequency of the internal clock specific to the xe2x80x9cCycle Masterxe2x80x9d node.
The duration of the cycle T is thus for example equal to 125 microseconds.
When two serial communication buses are connected by a bridge, the xe2x80x9cCycle Masterxe2x80x9d of one of the buses must synchronize its cycles in relation to the cycles generated by the xe2x80x9cCycle Masterxe2x80x9d of the adjacent bus.
The xe2x80x9cNet Cycle Masterxe2x80x9d node will then generate on the bus, every 125 microseconds, a so-called xe2x80x9ccycle starxe2x80x9d signal.
This signal intended for the other nodes of the bus informs them that they can send their isochronous data packet associated with each cycle of the bus under consideration, to one or more of the other buses which are connected to the said bus under consideration respectively by one or more bridges.
Furthermore, the specifications of the 1394 standard indicate that the internal clock frequency of a 1394 peripheral must be 24.576 MHz+/xe2x88x92100 ppm which allows, at maximum, a difference of two internal clock cycles every 3 cycles of the bus between two 1394 peripherals.
The maximum difference is in fact obtained when the internal clock frequency of one of the peripherals is 24.576 MHz+100 ppm and the other frequency of the other peripheral is 24.576 MHzxe2x88x92100 ppm.
For example, the frequency of the internal clock specific to the xe2x80x9cNet Cycle Masterxe2x80x9d denoted by CMA has a value of 24.576 MHz+100 ppm, while that of the internal clock specific to the xe2x80x9cCycle Masterxe2x80x9d CMB of a lower level bus which is directly connected to the upper level bus by a bridge has a value of 24.576 MHzxe2x88x9250 ppm.
The communication networks formed from serial communication buses allow the transmission of packets synchronized from the cycles of the buses under consideration. The buses are for example used for transmitting audio/video type data packets in real time.
Thus, when the two xe2x80x9cCycle Mastersxe2x80x9d mentioned previously, denoted by CMA and CMB, are taken, with their respective clock frequency values, namely 24.576 MHz+100 ppm and 24.576 MHzxe2x88x9250 ppm, the durations of the cycles calculated for each of the said xe2x80x9cCycle Mastersxe2x80x9d, denoted respectively by TA and TB, are different on account of the different frequencies of the internal clocks specific to these xe2x80x9cCycle Mastersxe2x80x9d.
FIG. 1 moreover illustrates this phenomenon and shows, on two superposed axes, for one and the same integer number ninit such that TA=ninit/FA and TB=ninit/FB, where F designates the dock frequency of the xe2x80x9cCycle Masterxe2x80x9d under consideration, a cycle of duration TB greater than the cycle TA.
In this figure there are depicted, above the first two cycles of the bus, the numbers of two data packets identified by the numbers 1 and 2.
It should also be noted that the case depicted in FIG. 1 is highly improbable in reality since it envisages a null phase displacement at the beginning of each of the first cycles of the two buses.
However, comparison of these two axes reveals a relative drift of the starts of each cycle which corresponds in fact to a change in the phase displacement (null at the time origin in the figure) over time between the cycles under consideration.
Furthermore, two arrows have been depicted between the two axes to indicate the delay with which the data packets denoted by 1 and 2 are transmitted on the bus B after having passed over the bridge interconnecting the buses A and B. It is estimated in effect that the delay depicted here is equivalent to two cycles and is explained by the time necessary for processing the packets in the bridge before their transmission on the bus B.
Thus, in view of the relative time drift noted between the respective cycles of the buses A and B, at the end of a certain number of cycles, a data packet coming from the bus A will not be transmitted at the bus B.
The non-transmission of this data packet therefore risks being highly detrimental for real time data of the audio and/or video type.
This is because, with data for example of video type, it is very important to transmit all the video data packets correctly in order not to degrade the video image obtained from the transmitted packets.
Generally, if it is noted that the duration TA is less than TB, then one data packet will be lost at the end of a certain number of cycles, which means that one cycle will have been lost and if, on the contrary, TA is greater than TB, then no data packet will be transmitted during one of the cycles and there will therefore be a cycle devoid of any significance, leading, through that very occurrence, to a loss of synchronization in the processing of audio and/or video type data in real time.
The detection of a relative drift between the cycles which will subsequently be responsible for a lost cycle or one cycle too many is carried out in each bridge, for a given cycle, by counting simultaneously, with the help of registers, the numbers of pulses generated by the clocks of the two buses under consideration and for example comparing these two numbers with one another at regular time intervals.
In order to remedy the drift problem, the P13941 standard makes provision, as soon as a drift is detected at the level of the bridge, to send, to the xe2x80x9cCycle Masterxe2x80x9d CMB, a message transmitting a command for modification in consequence of the integer number ninit of dock pulses, in order to make the cycle durations TA and TB coincide.
It should be noted that this resynchronization is carried out only in pairs of buses.
By way of example, the network of the type of that depicted in FIG. 2 has the serial communication buses denoted by A, B, C, D and E which are interconnected in pairs by a bridge: the buses A and B, B and C, C and D, D and E are respectively interconnected by the bridges P1, P2, P3 and P4. Furthermore, the buses A, B, C, D and E each have a xe2x80x9ccycle masterxe2x80x9d denoted respectively by CMA, CMB, CMC, CMD and CME.
Detecting the drifts between each pair of buses connected by a bridge, the Applicant has made the following observations: there will be one cycle too many every four cycles between the buses denoted by A and B, one cycle will be lost every eight cycles between the buses denoted by B and C, no drift is detected between the cycles of the buses denoted by C and D, and one cycle will be lost every eight cycles between the buses denoted by D and E.
Therefore, in conforming to the standard mentioned above, the Applicant realized that a number of modification messages to be executed might well arrive at the same xe2x80x9cCycle Masterxe2x80x9d of a lower bus of the network.
For example, the xe2x80x9cCycle Masterxe2x80x9d CMB of the bus B will receive a synchronization command for modifying the duration of its cycle telling it to increase the counting of the number of pulses generated by its clock by one unit, around once every four cycles.
The xe2x80x9cCycle Masterxe2x80x9d CMC of the bus C will receive two commands for modifying the duration of its cycle: one corresponding to the propagation of the command mentioned previously and received by the xe2x80x9cCycle Masterxe2x80x9d of the bus B, the other corresponding to a command for modifying the duration of its cycle telling it to increase the number of pulses generated by its clock by one unit in order to balance out the drift detected between the cycles of the buses B and C. This is because the sending of the synchronization commands for bringing forward (xe2x80x9cgo-fastxe2x80x9d) or putting back (xe2x80x9cgo-slowxe2x80x9d) the start of the following cycle is carried out by the portal of the bridge which has detected the drift in relation to the adjacent bus. This portal is also referred to as the xe2x80x9cSlave Portalxe2x80x9dor xe2x80x9cClock Masterxe2x80x9d.
The reaction time, at the level of the bus on which a number of modification messages arrive, between the time the messages are received by the xe2x80x9cCycle Masterxe2x80x9d concerned and the time they are processed, increases with the number of messages to be processed and therefore with the decreasing level of the bus in the network hierarchy. Thus not all buses of the network enjoy the same time stability on account of their hierarchy.
Moreover, it may be that messages are conflicting and nothing is provided for checking this point
Furthermore, the higher the number of synchronization messages, the more the passband of the bus is reduced. Thus the lower level buses have less passband available for data transmission than those of the higher level buses.
The exaggeration of the phenomenon at the lower levels of the network can result in failure of the synchronization of the cycles of the different buses and therefore probably in the loss of data.
The present invention thus aims to remedy at least one of the above-mentioned problems by proposing a method of controlling the synchronization in a data packet communication network having at least two serial communication buses interconnected by a bridge and each defining successive time cycles each having a duration specific to the said bus under consideration, the said method having the following steps:
detection of a relative drift between the respective cycles of the said at least two serial communication buses,
transmission of a command for modifying the duration of the cycle of one of the said at least two serial communication buses, characterised in that the said method includes at least one delay phase before at least one of the preceding steps.
Thus, the invention makes provision for waiting, during a delay phase, before undertaking an action of either detecting a drift or transmitting a synchronization command when such an action is necessitated by circumstances. Synchronization command means a command for modifying the duration of the cycle of one of the serial communication buses.
This allows the drifts which occur during this phase to balance one another out xe2x80x9cnaturallyxe2x80x9d or to add up without undertaking, at each cycle, one or more actions which would not be essential. The drifts are thus allowed to progress naturally for a duration which may be dictated by the earlier results and/or by other reasons connected with the bridge under consideration.
According to one characteristic, the delay phase has a duration which extends over a number of cycles.
According to a first embodiment of the invention, the delay phase starts after the step of detecting a relative drift between the respective cycles of the said at least two serial communication buses.
Thus, instead of transmitting a command for modifying the duration of the cycle of one of the two serial communication buses as soon as a non-null relative drift is detected between the respective cycles of the said buses, the invention makes provision for waiting before undertaking any modification command transmission.
This makes it possible, as soon as a non-null drift is detected, to not systematically call upon the passband of the bus for transmitting a synchronization command.
According to one characteristic, the delay phase has a number of detection steps.
Each detection step takes place for a given cycle.
By delaying for a short while any action of modifying the duration of a cycle as soon as a non-null drift is detected, benefit can thus be obtained from the xe2x80x9cnaturalxe2x80x9d balancing out between this drift and one or more other drifts detected before and/or after this one during one and the same delay phase.
The number of modifications, sometimes conflicting, of the duration of the bus cycles can thus be significantly reduced.
Therefore, the lower level buses are in transmission conditions identical to those of the upper level buses.
Similarly, with the bridges being less often called upon for transmitting commands to the buses with a view to reducing or increasing the duration of their cycle, the said bridges regain in efficiency by thus optimizing their internal processing time.
According to a particular characteristic, the invention provides a step of storing the drift which has just been detected.
According to a particular characteristic, the step of storing the detected drift includes an operation of summing the said detected drift with a stored drift for an earlier cycle.
Thus, the latest detected drift is added to the sum of the successive drifts previously detected at the level of the same bridge. This makes it possible to continuously monitor the change in the summed drift over time.
Moreover, the summing of the various null or non-null drifts detected during the cycles of the delay phase may give rise, at the end of the said phase, by virtue of the xe2x80x9cnaturalxe2x80x9d balancing out, to a null stored drift.
Thus, it is no longer necessary to transmit a command for modifying the duration of the cycle of one of the buses.
However, the summing operation is not obligatory in order to know, or at least in order to be able to estimate, the detected drift at the level of a bridge over a number of successive cycles.
This is because, in this case the detected drift for a cycle is stored without summing it with the earlier drifts. For example, the application can be envisaged of digital processing related to the change over time of variations in the detected drift in order to better manage the transmission of cycle duration modification commands.
According to this first embodiment, the method according to the invention includes a step of comparing the stored drift with a predetermined threshold, this threshold corresponding to a value of the drift for which, or beyond which, it is mandatory to carry out a modification of the duration of the cycle of one of the serial communication buses.
This threshold is determined as a function of the results noted during the earlier delay phases and, for example, the results noted on the storing of the drifts.
This threshold is positive or null, or negative or null, according to circumstance, in order to take account of positive values (bringing forward the clock of one of the buses in relation to the clock of the other bus) or negative values (putting back the clock of one of the buses in relation to the clock of the other bus) of the detected and stored drifts.
It is of course favourable to have two thresholds, one positive, in order to avoid drifts which are too large in bringing forward clocks with respect to one another, and the other negative in order to avoid drifts which are too large in putting back clocks with respect to one another.
Thus, when the stored drift is greater in absolute value than the absolute value of the predetermined threshold, then the delay phase comes to an end.
In this embodiment where the stored drift is compared with a predetermined threshold, the delay phase has a duration which extends over a number of cycles which is not determined in advance since it is not known whether drifts are going to be detected for the cycles to come.
According to another characteristic, when the delay phase comes to an end and the stored drift is greater in absolute value than the absolute value of the predetermined threshold, the method includes at least one step of transmitting at least one command for modifying the duration of the cycle of one of the said at least two serial communication buses. It is for example possible that the envisaged modification is proportional to the stored drift.
However, by way of a variant, it is also possible to transmit a command as long as the stored drift is not null.
According to a particular characteristic, the method includes a step of decrementing the absolute value of the stored drift by a value adapted to the modification of the duration of the cycle of one of the said at least two serial communication buses.
This value is thus, for example, proportional to the stored drift in the aforementioned case.
It should be noted that, when the delay phase comes to an end and the stored drift is null, then the method according to the invention makes provision to not institute a step of transmitting a command for modifying the duration of the cycle of one of the buses.
According to a first variant of the first embodiment, the delay phase extends over a predetermined number of cycles allocated to the bridge under consideration.
In this variant embodiment, it is detected whether null or non-null drifts arise throughout these cycles without transmitting a command for modifying the duration of the cycle of one of the buses.
It is only when the predetermined number of cycles is reached that at least one synchronization command is transmitted.
According to a particular characteristic, the communication network having a number of serial communication buses interconnected by bridges and forming a structure with a tree hierarchy from a so-called xe2x80x9crootxe2x80x9d bus, the predetermined number of cycles allocated to a bridge depends on the position of the said bridge in the structure with a tree hierarchy.
Thus, for example, the further away the bridge is from the xe2x80x9crootxe2x80x9d bus in the network structure with a tree hierarchy, the larger is this number.
This is because, the further away the bridge is from the xe2x80x9crootxe2x80x9d bus, the higher the risk of receiving a number of commands, sometimes conflicting, for modifying the duration of the cycle of a bus.
Consequently, monitoring the change in the drifts detected at the level of the bridge under consideration over a certain number of cycles, it is highly probable that the successively detected drifts will balance one another out over time.
This will therefore make it possible to save, as it were, on the number of commands for modifying the duration of the cycle of the bus under consideration to be transmitted.
Furthermore, the predetermined number of cycles allocated to the bridge under consideration can also, or by way of an alternative, depend on the drift detected during at least one earlier delay phase.
It should be noted that a second variant of the first embodiment can be envisaged which uses again the two embodiments which have just been mentioned.
It is a question in this second variant of having an adaptable delay phase which can either extend at most over the predetermined number of cycles mentioned above, or extend over a smaller number of cycles where the summed drifts cross one of the predetermined thresholds.
More particularly, the duration T of a cycle specific to a serial communication bus being determined by a number ninit of clock pulses generated by the internal clock of the said bus during this cycle according to the relationship T=ninit/F, where F designates the frequency of the clock under consideration, the step of detecting the relative drift between the respective cycles of the clocks of the said at least two serial communication buses consists of comparing, with one another, the numbers of pulses generated by the said clocks.
The serial communication buses are for example in accordance with the IEEE 1394 standard, which is advantageous, since the aim of this standard is to combine the interconnection of all multimedia type peripherals in the years to come.
According to a second embodiment of the invention, the delay phase comes to an end before the step of detecting a relative drift between the respective cycles of said at least two serial communication buses.
The Applicant having realized that it is neither essential to undertake an action of detecting a drift at each cycle, nor to transmit a command for modifying the duration of the cycle of one of the buses connected to the bridge under consideration at each cycle, during the delay phase it is waited for the drifts to balance one another out or add up before detecting them.
At the end of the delay phase, it may be that the drifts have balanced one another out in which case the detection step leads to a null drift or one so small that it does not require transmission of a synchronization command. The choice can then be made either to let another similar delay phase continue before instituting a new detection step, or to let a new delay phase elapse before transmitting a synchronization command, but detecting, at each cycle of this new delay phase, the null and non-null drifts which occur.
The other possible case, at the end of the delay phase, is that the drifts have accumulated without balancing out.
In this case it may be decided, for example, to carry out at least one step of transmitting a synchronization command if the detected drift is judged too large.
The modification of the duration of the cycle of one of the buses (synchronization) is, for example, proportional to the detected drift.
However, by way of a variant, it is also possible to transmit a command for modifying the duration of a cycle of one of the buses as long as the detected drift is not null.
It can also be envisaged, if the detected drift is not too large, either to let another similar delay phase continue before carrying out a new detection step, or to let a new delay phase elapse before transmitting a synchronization command, but detecting, at each cycle of this new delay phase, the drifts which occur.
According to a particular characteristic related to this second embodiment, when the delay phase comes to an end and a non-null drift is detected, the said method includes a step of comparing the detected drift with a predetermined threshold in order to determine whether it is mandatory that the detected drift requires the transmission of a synchronization command.
The characteristics specific to this threshold are the same as those described above for the first embodiment of the invention.
According to a particular characteristic, when the detected drift is greater in absolute value than the absolute value of the predetermined threshold, then the said method includes at least one step of transmitting at least one command for modifying the duration of the cycle of one of the said at least two serial communication buses.
The modification of the duration of the cycle of one of the buses (synchronization) is, for example, proportional to the detected drift.
However, by way of a variant, it is also possible to transmit a command for modifying the duration of the cycle of one of the buses as long as the detected drift is not null.
As mentioned previously, when a first delay phase has elapsed and a step of detecting a drift has been carried out, it is possible, provided that the drift is not too large, either to let another similar delay phase continue before instituting a new detection step, or to let a new delay phase elapse before transmitting a synchronization command, but detecting, at each cycle of this new delay phase, the null and non-null drifts which occur.
In each of these two cases, either the detected drift is stored once only and the end of the similar delay phase is waited for, for detecting any drift and storing it, or each detected drift is stored during this new delay phase.
Furthermore, in the two cases envisaged, the step of storing each detected drift can include an operation of summing the latter with a stored drift for an earlier cycle.
Following the summing, either the stored drifts have balanced one another out or they have accumulated, and the method according to the invention then includes a step of comparing the stored drift with a predetermined threshold in order to determine whether it is mandatory that this drift requires the transmission of a synchronization command.
The characteristics of this threshold are the same as those described above for the first embodiment.
According to one characteristic, when the stored drift is greater in absolute value than the absolute value of the predetermined threshold, then the delay phase comes to an end.
The method then includes at least one step of transmitting at least one command for modifying the duration of the cycle of one of the said at least two communication buses.
The modification of the duration of the cycle of one of the buses (synchronization) is, for example, proportional to the stored drift.
However, by way of a variant, it is also possible to transmit a command for modifying the duration of the cycle of one of the buses as long as the stored drift is not null.
According to a particular characteristic, the method includes a step of decrementing the absolute value of the stored drift by a value adapted to the modification of the duration of the cycle of one of the said at least two serial communication buses.
This value is thus, for example, proportional to the stored drift in the aforementioned case.
On the other hand, when the stored drift is null, then the method according to the invention makes provision to not institute a step of transmitting a command for modifying the duration of the cycle of one of the buses.
Generally, the characteristics and advantages described for the first embodiment remain the same for the second embodiment.
Correlatively, the invention relates to a device for controlling the synchronization in a data packet communication network having at least two serial communication buses interconnected by a bridge, the said bridge providing the interface between the said at least two serial communication buses, which each define successive time cycles each having a duration specific to the said bus under consideration, the said device having:
means of detecting a relative drift between the respective cycles of the said at least two communication buses,
means of transmitting a command for modifying the duration of the cycle of one of the said at least two serial communication buses, characterised in that the said device has means of delaying at least one of the actions of detecting a drift and transmitting a command for modifying the duration of a cycle.
According to one characteristic, the device more particularly has means of delaying an action of transmitting a command for modifying the duration of a cycle.
According to one characteristic, the device more particularly has means of delaying an action of detecting a relative drift between the respective cycles of the said at least two communication buses.
According to one characteristic, the device has means of transmitting a command for modifying the duration of the cycle of one of the said at least two serial communication buses.
The modification is, for example, proportional to the detected drift.
According to a second aspect, the invention relates to a bridge providing the interface between at least two serial communication buses in a data packet communication network, characterised in that the said bridge has a device for controlling the synchronization in this network such as briefly described above.
According to a third aspect, the invention relates to data processing equipment, characterised in that it has a bridge in accordance with the preceding brief description.
The processing equipment is, for example, a printer.
The processing equipment is, for example, a server.
The processing equipment is, for example, a computer
The processing equipment is, for example, a facsimile machine.
The processing equipment is, for example, a scanner.
The processing equipment is, for example, a video recorder.
The processing equipment is, for example, a decoder (known by the term xe2x80x9cset top boxxe2x80x9d).
The processing equipment is, for example, a television.
The processing equipment is, for example, a video camera.
The processing equipment is, for example, a digital camera.
The processing equipment is, for example, digital photographic equipment.
According to a fourth aspect, the invention relates to a data packet communication network having at least two serial communication buses interconnected by a bridge, characterised in that the said bridge is in accordance with the above.
According to a fifth aspect, the invention relates to a data communication network having at least two serial communication buses interconnected by a bridge, characterised in that the said network has data processing equipment such as briefly described above.
The invention furthermore relates to an information storage means, possibly totally or partially removable, readable by a computer or a processor containing instructions of a computer program, characterised in that it allows the implementation of the method of controlling the synchronization in a network such as briefly described above.
The invention also relates to an information storage means readable by a computer or a processor containing data resulting from the implementation of the method of controlling the synchronization in a communication network such as briefly described above.
The invention also relates to an interface making it possible to receive the instructions of a computer program, characterised in that it allows the implementation of the method of controlling the synchronization in a network such as briefly described above.
The invention also relates to a computer program product loadable into a programmable device, comprising software code portions for performing the steps of the method of controlling the synchronization in a communication network such as briefly described above when said product is run on a programmable device.
Since the advantages and characteristics specific to the device for controlling the synchronization in a communication network, to the bridge providing the interface between at least two serial communication buses and having such a device, to the data processing equipment having such a bridge, to the said network having such a bridge and to the said network having such data processing equipment, as well as to the information storage means, are the same as those described above concerning the method of controlling the synchronization in a communication network according to the invention, they will not be repeated here.